Arrangement and method for adjustment of the slope times for one or more drivers and a driver circuit

ABSTRACT

The invention relates to an arrangement ( 10 ) and a method for adjusting the slope times of one or more drivers ( 90 ) in such a way that the adjustment is essentially independent of external conditions. The invention also relates to a driver circuit. The arrangement ( 10 ) is provided with a device ( 20 ) for detecting the time history of an output voltage that is output and supplied to a load ( 12 ) by means of the driver/s ( 90 ). The measured time values are converted into an output voltage value in a device ( 30 ) for converting the measured time history of the output voltage. Moreover, a device ( 40 ) for generating a reference voltage value is provided. Said device ( 40 ) is connected to a device ( 60 ) for predetermining a desired slope time for the driver/s ( 90 ), whereby said slope time is essentially independent of external conditions. A system pulse can be partitioned into differently long rectangular pulses in the device ( 60 ) in such a way that the user of the arrangement ( 10 ) can select from the group of said rectangular pulses which match certain slope times respectively. The output voltage value and the reference voltage value are compared in a comparing device ( 50 ) that is also connected to the driver/s ( 90 ) in such a way that said driver/s ( 90 ) can be readjusted thereby.

[0001] The present invention relates first of all to an arrangement andto a method for adjustment of the slope times for one or more driversessentially independently of external conditions. The invention alsorelates to a driver circuit and to advantageous applications.

[0002] Drivers and driver circuits are known, for example, as paddrivers for integrated circuits such as microcontrollers,microprocessors, ASICs, memory modules or the like and, to a majorextent, govern the electromagnetic compatibility (EMC) of digitalassemblies, for example of controller devices for motor vehicle orautomation technology.

[0003] The relatively large current transients (dI/dt) which arerequired in order to charge and to discharge the generally capacitiveloads, which are connected to the drivers, in a relatively short time toa specific voltage potential are a critical factor for such drivers anddriver circuits. These times, which are referred to as the rise times(trise) and fall times (tfall) relate to the respectively rising andfalling slope and are quoted for a specific maximum load in thespecification for the driver. Normally, the driver strength is designedsuch that the driver comprises the guaranteed driver and timingcharacteristics in the worst permissible environmental conditions(referred to as the worst case).

[0004] For CMOS circuits, which are known per se, such worst caseconditions are, for example, high ambient temperatures, low operatingvoltages, poor production parameters, that is to say productionparameters which lead to “slow” switching times, and a maximum load, orthe like. Since worst case conditions generally occur only rarely, theoutput slopes of conventional drivers designed in such a way are verymuch steeper than necessary, thus making the disturbance spectrum worse.The slope times—rise time/fall time—are likewise not constant either,owing to the possibility of the environmental conditions changing.

[0005] An ideal driver in terms of electromagnetic compatibility has themaximum permissible slope times, which are independent of externalconditions, such as the ambient temperature, the operating voltage, theindividual production parameters, and the connected load or the like.Furthermore, the maximum permissible slope times are dependent on therespective application of the drivers. For example, memory buses requirea much shorter access time than, for example, input signals for anelectrical switch (referred to as a smart power switch).

[0006] Experiments have shown that a significant improvement in theelectromagnetic compatibility of output drivers can be achieved byreducing the driver strength and, associated with this, by increasingthe slope times.

[0007] There is thus a need to be able to adjust the slope times ofdrivers individually.

[0008] DE-A-44 415 23 C1 discloses a digital driver circuit for anintegrated circuit, in which the driver circuit can be matched to aspecific application by the operator himself. Depending on the nature ofthe application, in this case depending on the load capacitance of acomponent which is to be operated using the driver circuit, thisoperator must enter an appropriate figure in an input apparatus. Thefigure is a variable which is dependent on the application. Physically,this circuit is a controller. The known solution assumes that variationsin the environmental conditions can be established unambiguously bymeasuring the saturation current of a measurement transistor.

[0009] EP-A-0 436 316 A1 also specifies a circuit arrangement, whichmatches the impedance of a driver to a connected network. In this case,the circuit arrangement is intended to be suitable for being able tomatch itself to a load with an initially unknown impedance. To do this,the circuit arrangement has a driver with a predetermined impedance. Anelement for optional selection of an impedance is connected to thedriver and, on operation, selectively causes changes to thepredetermined impedance to match a desired, different impedance of theconnected load. A further element is connected to this element forselection of the impedance. This element measures the impedancedifference between the output of the driver and a digital circuit whichis connected to it. A suitable impedance is selected on the basis of themeasured values from the element for selection of the impedance, and isadded to the predetermined, impedance, that is to say the presetimpedance of the driver.

[0010] One object of the present invention is to provide an improvedarrangement, and a method for adjustment of slope times for one or moredrivers, as well as an improved driver circuit, by means of which, inparticular, the slope times for one or more drivers can be adjusted in asimple manner, and essentially independently of external conditions.

[0011] According to the first aspect of the invention, this object isachieved by an arrangement for adjustment of the slope times for one ormore drivers essentially independently of external conditions, having anapparatus for recording the time profile of an output voltage which isemitted from the driver or drivers to a load, having an apparatus forconversion of the measured time profile of the output voltage to anoutput voltage value, having an apparatus for production of a referencevoltage value, having a device for presetting a desired slope time,which is essentially independent of external conditions, for the driveror drivers, which device is connected to the apparatus for production ofa reference voltage value, and having a device for comparison of theoutput voltage value with the reference voltage value, in which case thecomparison device is or can be connected to the driver or drivers.

[0012] The arrangement according to the invention makes it possible toadjust the slope times for drivers independently of external conditions.In particular, it is possible to adjust the slope times for the driversindependently of the temperature, operating voltage, production processand load. These external conditions are enumerated purely way ofexample, so that the slope times can also be adjusted independently ofother external conditions which are not explicitly mentioned in thisenumeration.

[0013] The arrangement according to the invention means that one or moredrivers is or are calibrated by a control cycle, which can preferably berepeated, such that the user of such a driver can adjust and set desiredslope times, which can be selected within wide limits, largelyindependently of the external conditions.

[0014] The fundamental principle of the arrangement according to theinvention is to generate a reference voltage value which corresponds tothe desired slope time which can be programmed by the user. Thisreference voltage value is compared with an actually measured outputvoltage value. The driver or drivers is or are matched as a function ofthis comparison result.

[0015] When the driver or drivers is or are activated, the driver emitsan output voltage. This output voltage is passed to a load. If the loadwhich is connected to the driver or drivers is a load capacitance, thisload capacitance is charged to an operating voltage Vdd on the basis ofthe output voltage which is emitted from the driver or drivers. When thedriver or drivers is or are activated, the output voltage at the driveroutput will rise until the operating voltage Vdd is reached. Ananalogous situation applies to the converse case.

[0016] This time profile of the output voltage is recorded by theapparatus for recording the time profile, and this apparatus isspecified in more detail further on in the description.

[0017] Since, in general, time values can be compared with one anotheronly poorly, the measured time values are converted to an output voltagevalue in the apparatus for conversion of the measured time profile ofthe output voltage. This output voltage value can be temporarily stored.

[0018] At the same time, an appropriate reference voltage value isproduced in the apparatus for production of a reference voltage value,which will be explained in more detail further on in the description.The reference voltage value is produced in such a way that a desired,freely variable slope time, which is essentially independent of externalconditions, is preset for the driver or drivers via a device whichallows the user of the arrangement to preset a slope time. For thereasons mentioned above, this time signal is in turn converted to avoltage value, the reference voltage value. The reference voltage valuecan in turn be temporarily stored.

[0019] The output voltage value and the reference voltage value are thencompared with one another in the comparison device. This comparisondevice is likewise connected, or can be connected, to the driver ordrivers, so that the driver or drivers, or its or their driver strength,can be matched by means of the signals which are emitted from thecomparison device.

[0020] Preferred embodiments of the arrangement according to theinvention can be found in the dependent claims.

[0021] The arrangement according to the invention will be explained inthe following text with reference to an example, although, of course,the invention is not restricted to the specific example form. Thisspecific example form serves only to illustrate the relationships in thearrangement according to the invention.

[0022] This example assumes that, at the moment at which a driver inputchanges its state, the driver is switched such that a connected load,for example a load capacitance, is charged or discharged via a driveroutput line. In the following text, it is assumed that the driver inputsignal changes from low to high at the time t=0, which means that thepreviously discharged load capacitance is intended to be charged to theoperating voltage Vdd over the further course of time. An analogoussituation applies to the converse case.

[0023] The apparatus for recording the time profile of the outputvoltage emitted from the driver or drivers to a load may preferably bein the form of a window comparator.

[0024] This window comparator may advantageously have two voltagecomparators (CP1, CP2), which are connected to an AND gate.

[0025] The time profile of the output voltage at the driver output canbe monitored up to the operating voltage Vdd via a window comparatorsuch as this. The output of the window comparator may be switched tohigh, for example, during the rise time or the fall time of the voltagesignal.

[0026] The rise time, or the fall time, may, for example, be that timeperiod which a signal requires to change from 10% to 90% of the finalvoltage.

[0027] The two voltage comparators CP1, CP2 may, for example, bedesigned accordingly. One of the voltage comparators may, for example,produce a corresponding high signal once the voltage signal has exceededthe 10% mark of the final voltage. The other voltage comparator, may,for example, emit a high signal until the voltage signal has reached the90% mark of the final voltage. The two signals from the respectivevoltage comparators are joined together in the AND gate. When bothvoltage comparators produce a high signal, the voltage signal which isemitted from the driver is in its rise time, or in its fall time.

[0028] In terms of formulae, the output of the window comparator is thushigh when:

fu*Vdd<Vout<fo*Vdd,

[0029] where, for example, fu=0.1, fo=0.9, Vdd=operating voltage andVout=output voltage.

[0030] In a further refinement, the apparatus for conversion of themeasured time profile of the output voltage to an output voltage valuemay have a current source, a switch element and a capacitance, in whichcase the switch element is operated or can be operated via signals fromthe apparatus for recording the time profile of the output voltage whichis emitted from the driver or drivers to a load.

[0031] The measured time value is converted to a voltage value in thisapparatus. To do this, the switch element may, for example, be closedduring the high state of the apparatus in order to record the timeprofile of the output voltage (advantageously of the window comparator),by which means a previously discharged capacitance (for example ameasurement capacitance Cmeas) is charged by means of the current sourceto an output voltage value (Vmeas).

[0032] The apparatus for production of a reference voltage value mayadvantageously have a current source, a switch element and a referencecapacitance, in which case the switch element is operated or can beoperated via signals from the device for presetting a desired slope timefor the driver or drivers. A structure such as this allows the referencecapacitance (Cref) to be charged to a reference voltage value (Vref) inthe manner described above.

[0033] The period during which the switch element is closed is preset bythe user of the arrangement by operating the device for presetting adesired slope time, which is essentially independent of externalconditions, for the driver or drivers, which device will be explained inmore detail further on in the description. The time period during whichthe switch element is closed thus corresponds to the desired rise time,or fall time.

[0034] In a further refinement, the device for comparison of the outputvoltage value with the reference voltage value may be in the form of acomparator. This voltage comparator (CP3) compares the output voltagevalue (Vmeas) with the reference voltage value (Vref). When Vmeas<Vref,the capacitance for the output voltage has been charged for a shortertime than the reference capacitance. The actual rise time, or fall time,was accordingly shorter than that desired. The voltage comparator (CP3)can indicate this, for example, by outputting a high level, thusreducing the driver capability of a connected driver. An analogoussituation applies to the case where Vmeas>Vref.

[0035] The control cycle starts once again on the next rising or fallingslope, so that the driver is successively matched to the load and to thedesired slope time.

[0036] An apparatus for selection of the driver strength can preferablybe provided, with this apparatus being connected to the device forcomparison of the output voltage value with the reference voltage value,and in which case the apparatus for selection of the driver strength isor can be connected to the driver or drivers as well. The apparatus canbe connected to the driver or drivers via appropriate control lineswhich are referred to, for example, as a driver enable bus (DEB).

[0037] The device for presetting the desired slope time for the driveror drivers can preferably be designed to produce a square-wave pulse,whose length corresponds to the desired slope time.

[0038] The essential feature for the quality of the driver regulation,or driver adjustment, is the exact generation of the desired slope time.This must not be dependent on external conditions, such as variations inthe production process, fluctuations in the ambient temperature, themagnitude of the supply voltages or the like. On-chip circuits are verylargely impractical for this purpose, since they are subject to theseinfluences and compensation would involve major complexity.

[0039] It is therefore advantageously possible to provide for the devicefor presetting the desired slope time for the driver or drivers to bedesigned for processing a system clock. A system clock such as this isavailable, for example, in microcontrollers, microprocessors and in mostASICs. The system clock is generally generated from an external crystal,or oscillator, and may be assumed to be constant with regard to thestated external conditions.

[0040] If the clock frequency of the system clock is equal to fmc(mc=master clock), then the pulse length t=1/(2*fmc) can be tapped offdirectly. Different pulse widths of duration t=2{circumflex over( )}n/(2*fmc) where n>0 can be produced by means of frequency dividers.

[0041] If pulse lengths such that t<1/(2*fmc) are required, so-calledphase locked loop circuits may be used. It is likewise possible to use acircuit which has the features described in the following text.

[0042] The device for presetting the desired slope time for the driveror drivers may preferably have one or more delay elements. Each delayelement delays the output of the rising slope at its output as afunction of a control voltage (Vctrl). The input signal is, for example,a relatively low-frequency system clock which, when a number of delayelements are used, passes through a delay line formed by such delayelements.

[0043] Furthermore, the device for presetting the desired slope time forthe driver or drivers may have at least one phase detector. A phasedetector such as this checks whether the falling slope of the inputsignal (master clock) occurs at the same time as the rising slope, whichis emitted with the delay, at the output from the delay line.

[0044] If this is not the case, depending on which level change tookplace first, the control voltage is changed such that the phasedifference becomes less in the next cycle. An apparatus for productionof such a control voltage may be provided, for example, in order toproduce the control voltage.

[0045] The falling slope of the input signal may be passed on virtuallywithout any delay by the delay element, or by the delay elements. If theinput signal is in each case linked to the output of each delay elementvia appropriate AND gates, the input signal itself results in n parallelsignals which have high level durations of tmin, 2*tmin, 3*tmin, . . . ,n*tmin, where n=the number of delay elements, and tmin=1/(2*n*fmc).

[0046] The device for presetting the desired slope time for the driveror drivers may advantageously have at least one switch element, inparticular a multiplexer, for switching between different slope signals.This switch element allows the user to select a signal which he desiresand which then corresponds to the desired slope time. The switch elementis preferably in the form of a multiplexer. Multiplexers such as theseare already known per se. They have a decoder which may select a desiredone of n inputs, which is then passed to an output. Multiplexers can beproduced both with gates and with analog switches using CMOS technology.

[0047] A configuration such as this of the device for presetting thedesired slope time for the driver or drivers first of all makes itpossible to compensate for fluctuations in the external conditions in amanner which is simple but nevertheless very accurate. Furthermore, adevice such as this has the advantage that there is a fixed and clearrelationship between the selected output pulse duration (slope time) andthe system clock frequency.

[0048] According to a second aspect of the present invention, a drivercircuit is provided for driving a load and has one or more drivers whichis or are connected to the load. This driver circuit is, according tothe invention, characterized in that the driver or drivers is or areconnected to an arrangement according to the invention as describedabove, for adjustment of the slope times.

[0049] The driver circuit according to the invention makes it possiblefor the driver or drivers to be calibrated by means of an—advantageouslyrepeating—control cycle in such a manner that the slope times which aredesired by the user and which can be selected within wide limits can beset or can be achieved largely independently of external conditions.With regard to the advantages, influences, effects and method ofoperation of the driver circuit according to the invention, reference islikewise made to the above statements relating to the arrangementaccording to the invention and to the following statements relating tothe method according to the invention, whose entire contents areexplicitly referred to here.

[0050] Preferred embodiments of the driver circuit can be found in thedependent claims.

[0051] The driver or drivers may preferably be in the form of a scalabledriver or scalable drivers.

[0052] Each driver may advantageously comprise one or more driverelements. The use of a number of driver elements is known per se and isdescribed, for example, in DE-195 45 904.0, which was likewise submittedby this applicant and whose disclosure content is to this extent alsoincluded in the description of the present invention.

[0053] If a scalable driver comprises a specific number of driverelements, preferably in parallel, these driver elements can be enabledor inhibited individually by means of control lines (driver enable busDEB). When the driver input changes its state, all the enabled driverelements switch in a corresponding manner and charge, or discharge, aconnected load via the driver line output.

[0054] The splitting of the driver into a number of partial driverelements has the further advantage that a high output impedance can beachieved at a low driver power level, and that, in consequence, it ispossible to reduce the extent to which disturbances are coupled onto thesupply lines. Furthermore, it is worthwhile to make the transistorwidths in each driver stage each twice as great as those in the nextlower stage. This means that it is possible to select the driver stagesby means of a driver strength selector in the form of a binary counter,so that the resultant driver strength range can be covered in equalsteps.

[0055] The increase or decrease in the driver strength after a controlcycle may in this case correspond, for example, to the driver strengthof the smallest driver stage.

[0056] One or more drivers may in each case advantageously be connectedto an arrangement for adjustment of the slope times. As has already beendescribed in the introduction, drivers are preferably used inconjunction with integrated circuits. Circuits such as these are, forexample, integrated on a chip, on which only a very small amount ofspace is normally available. In order to save chip surface area, fewerarrangements for adjustment of the slope times are preferably providedthan the number of drivers connected to them.

[0057] In this case, the individual drivers can each be connected to onearrangement via suitable switch elements, for example a multiplexer asalready described above. This makes it possible to successively regulatethe strengths of a number of output drivers, which are advantageouslyscalable, in the process of which the respective, optimum driverstrengths can be temporarily stored. Furthermore, a circuit arrangementsuch as this advantageously makes it possible for the regulation processto be carried out only in certain phases, for example the so-calledset-up phases, and for the driver strengths which have been found thento be checked at suitably selected time intervals.

[0058] The load which is connected to the driver or drivers mayadvantageously be in the form of a capacitive load. This is the mostfrequent configuration form of such loads, particularly in the field ofCMOS circuits. Nevertheless, the invention is not restricted tocapacitive loads, so that resistive or inductive loads as well as anydesired combinations of the individual load types are feasible in allcases.

[0059] According to a third aspect of the present invention, a method isprovided for adjustment of the slope times for one or more driversessentially independently of external conditions, which method can becarried out, in particular, using an arrangement according to theinvention as described above. This method is characterized by thefollowing steps:

[0060] a) measurement of the time profile of an output voltage which isemitted from the driver or drivers to a load;

[0061] b) conversion of the measured time profile of the output voltageto an output voltage value;

[0062] c) production of a reference voltage value which is essentiallyindependent of external conditions;

[0063] d) comparison of the output voltage value with the referencevoltage value; and

[0064] e) matching of the driver or drivers as a function of thecomparison results.

[0065] The method according to the invention allows the driver ordrivers to be calibrated in a simple manner such that slope times whichare desired by the user and can be selected within wide limits can beachieved or set largely independently of external conditions. Withregard to the advantages, influences, effects and method of operation ofthe method according to the invention, reference is likewise made to theabove statements relating to the arrangement according to the inventionand to the driver circuit according to the invention, whose entirecontents are explicitly referred to here.

[0066] Advantageous embodiments of the method can be found in thedependent claims.

[0067] The fundamental principle of the method according to theinvention is to generate a reference voltage value which corresponds tothe programmable slope time which is desired by the user. This referencevoltage value is compared with an actually measured output voltagevalue. The driver is matched as a function of this comparison result.

[0068] The time profile of the output voltage can advantageously bemeasured by measuring its rise time and/or its fall time.

[0069] The measured time profile of the output voltage can preferably beconverted in an apparatus for conversion to an output voltage value.This is advantageous since voltage values can be compared considerablymore easily and accurately than would be possible in the case of timevalues.

[0070] The apparatus for conversion of the time profile of the outputvoltage may advantageously have a current source, a switch element and acapacitance, with the time profile of the output voltage being convertedto an output voltage value by closing the switch element during apredetermined time period, in particular during the rise time and/or thefall time of the output voltage, and such that, during this time period,the previously discharged capacitance is charged by means of the currentsource to the output voltage value.

[0071] In a further refinement, the reference voltage value can beproduced in an apparatus for production of a reference voltage value,with the apparatus having a current source, a switch element and areference capacitance, by the switch element being closed via a devicefor presetting a desired slope time, which is essentially independent ofexternal conditions, for the driver or drivers for the duration of avoltage pulse, in particular a square-wave pulse, which is preset by thedevice and whose length corresponds to the desired slope time, and,during this time period, with the previously discharged referencecapacitance being charged by means of the current source to thereference voltage value.

[0072] The output voltage value and the reference voltage value may becompared in a comparator, with the slope time of the output voltageswhich are emitted to the load being adjusted on the basis of thesecomparison results.

[0073] The individual method steps can be repeated in order to produce acontrol cycle. In this case, the driver strength of each driver is ineach case matched with a delay of one clock cycle. However, this isgenerally not disadvantageous since the external conditions normallychange only slowly.

[0074] An arrangement according to the invention and as described abovefor adjustment of one or more drivers and/or a driver circuit accordingto the invention as described above and/or a method according to theinvention as described above may particularly advantageously be used inconjunction with integrated circuits, with the individual driverspreferably being in the form of pad drivers.

[0075] The invention will now be explained in more detail usingexemplary embodiments with reference to the attached drawings, in which:

[0076]FIG. 1 shows a schematic circuit arrangement of a driver circuitaccording to the invention;

[0077]FIG. 2 shows a schematic circuit arrangement of a device forpresetting the desired slope time for the driver or drivers according tothe present invention; and

[0078]FIG. 3 shows a schematic circuit arrangement of a scalable drivercomprising a number of partial driver elements.

[0079]FIG. 1 shows a driver circuit which, by way of example, isarranged on a chip 11 as a driver circuit for pad drivers for integratedcircuits. First of all, the driver circuit has an adjustable driver 90,which has a driver input 92 and a driver output 93. The driver 90 isconnected via the driver output 93 to a load, in the present case a loadcapacitance 12. For sake of clarity, FIG. 1 shows only a single driver90.

[0080] The driver 90 is connected via a control line (driver enable busDEB) to an apparatus 51 for selection of the driver strength, which isreferred to as a driver strength selector.

[0081] As is shown in FIG. 3, the adjustable driver 90 may be formedfrom a number of driver elements 91. Each driver element 91 is connectedto the driver strength selector 51 via a control line 52.

[0082] As can be seen from FIG. 1, the driver strength selector 51 is acomponent of an arrangement 10 for adjustment of the slope times for oneor more drivers 90. The arrangement 10 first of all has an apparatus 20for recording the rate of change of an output voltage and, in thepresent exemplary embodiment, this apparatus 20 is in the form of awindow comparator. The window comparator 20 is connected firstly to thedriver output 93.

[0083] The window comparator 20 has two voltage comparators CP1 and CP2,which are annotated by the reference numbers 21 and 22. The two voltagecomparators 21, 22 are connected to one another via an AND gate 23.

[0084] Furthermore, the arrangement 10 has an apparatus 30 forproduction of an output voltage value. The apparatus 30 has a currentsource 31, a switch element 32 and a capacitance Cmeas, which isannotated by the reference symbol 33. The switch element 32 may beoperated via signals which are emitted from the window comparator 20.

[0085] Furthermore, the arrangement 10 has an apparatus 40 forproduction of a reference voltage value. This apparatus 40 has a currentsource 41, a switch element 42 and a reference capacitance 43. Theswitch element 42 can be operated via signals from a device 60 forpresetting a desired slope time.

[0086] The two apparatuses 30, 40 for production of the output voltagevalue and of the reference voltage value, respectively, are connected toa voltage comparator CP3, which is annotated by the reference number 50.The voltage comparator 50 is likewise connected to the driver strengthselector 51.

[0087] The device 60, which is illustrated in FIG. 1, for presetting adesired slope time is described in more detail in FIG. 2. This device 60has a number of delay elements 61, which convert an input signal, in thepresent case a system clock 63, to square-wave pulses 62 with differentpulse lengths.

[0088] The individual delay elements 61 are combined to form a delaychain 68. A phase detector 64 and an apparatus 65 for production of acontrol voltage are also provided, for conversion of the voltage pulsesas will be explained in more detail with reference to the method ofoperation of the arrangement 10 according to the invention. The device60 furthermore has a number of AND gates 67. A desired square-wave pulse62 which corresponds to the desired slope time is selected via a switchelement 66 which may, for example, be in the form of a multiplexer.

[0089] The method of operation of the arrangement 10 for adjustment ofthe slope times for one or more drivers 90 essentially independently ofexternal conditions will now be described, in the following text.

[0090] The fundamental principle of the arrangement according to theinvention is the generation of a square-wave pulse 62 whose lengthcorresponds to the desired slope time, which can be programmed by theuser of the arrangement 10. The pulse length of the square-wave pulse 62is compared with the actual slope time, and the scalable driver 90 ismatched as a function of the result. The scalable driver 90 consists ofa number of parallel partial driver elements 91, which can be enabled orinhibited individually by means of control lines 52. When the driverinput 92 changes its state, all the enabled partial driver elements 91switch in a corresponding manner and charge, or discharge, the connectedload capacitance 12 via the driver output 93. In the following text, itis assumed that the driver input signal changes from low to high at thetime t=0, that is to say the previously discharged load capacitance 12is intended to be charged to an operating voltage Vdd over the furthercourse of time.

[0091] After the activation of the driver elements 91, which is enabledat this moment, the output voltage at the driver output will rise untilthe operating voltage Vdd is reached. This time profile is monitored bythe window comparator 20, which consists of the two voltage comparators21 and 22 and the AND gate 23. The output of the window comparatorswitches to high precisely during the rise time of the voltage signal,with the rise time being that time which the voltage signal requires tochange from 10% to 90% of the final voltage.

[0092] The time is now converted to a voltage value, by closing theswitch 32 in the apparatus 30 while the window comparator 20 is in thehigh state, as a result of which the previously discharged measurementcapacitance 33 is charged by means of the current source 31 to an outputvoltage value (Vmeas). The reference capacitance 43 is charged to areference voltage value (Vref) via an identical structure in theapparatus 40, with the current source 41, switch element 42 andreference capacitance 43. The period during which the switch element 42is closed is preset by the user via the device 60, and corresponds tothe desired rise time (slope time).

[0093] The voltage comparator 50 then compares the output voltage valuewith the reference voltage value. If Vmeas<Vref, the capacitance 33 forthe output voltage value has been charged for a shorter time than thereference capacitance 43, and the actual rise time has accordingly beenshorter than that desired. The comparator 50 will indicate this byoutputting a high level, as a result of which the driver capability ofthe adjustable driver 90 is reduced by the driver strength selector 51.An analogous situation applies to the case where Vmeas>Vref. The controlcycle starts once again for the next rising slope, so that the driver 90is successively matched to the load 12 and to the desired slope time.

[0094] The essential feature for the quality of the regulation is theexact generation of the desired slope time. This must not be dependenton external conditions. A system clock 63, which is available inmicrocontrollers, microprocessors or the like, is used for this reason,as is shown in FIG. 2. The system clock 63 may be assumed to be constantwith regard to external conditions.

[0095] The input signal is the relatively low-frequency system clock 63,which passes through a delay chain 68 formed by delay elements 61. Eachdelay element 61 delays the output of the rising slope at its input,depending on the control voltage produced in the apparatus 65. The phasedetector 64 checks whether the falling slope of the input signal 63occurs at the same time as the rising slope, which is emitted with thedelay, at the output of the delay chain 68. If this is not the case, thecontrol voltage is changed in the apparatus 65, depending on which levelchange took place first, such that the phase difference becomes smallerin the next cycle. The falling slope of the input signal 63 may bepassed on through the delay line 68 with virtually no delay.

[0096] If the input signal 63 is in each case linked to the output ofeach delay element 61 via corresponding AND gates 67, this results in nparallel signals, with the input signal 63 itself, in the form ofsquare-wave pulses 62. The user uses the switch element 66, which is inthe form of a multiplexer, to select from these a signal which is thenused as the square-wave pulse 62 for production of the reference voltagevalue.

[0097] This makes it possible to adjust slope times essentiallyindependently of external conditions. It is also advantageous that thereis always a fixed and clear relationship between selected output pulseduration 62 and the system clock frequency 63.

[0098] In order to make it possible to make optimum use of the surfacearea available on a chip 11, a number of drivers 90 may in each case beconnected to one and the same arrangement 10 for adjustment of the slopetimes. The drivers 90 may be connected to the arrangement 10 viasuitable switch elements, for example multiplexers, so that the drivers90 can be adjusted successively. The respective optimum driver strengthscan be temporarily stored in a suitable memory device, which is notillustrated.

1. An arrangement for adjustment of the slope times for one or moredrivers (90) essentially independently of external conditions, having anapparatus (20) for recording the time profile of an output voltage whichis emitted from the driver or drivers (90) to a load (12), having anapparatus (30) for conversion of the measured time profile of the outputvoltage to an output voltage value, having an apparatus (40) forproduction of a reference voltage value, having a device (60) forpresetting a desired slope time, which is essentially independent ofexternal conditions, for the driver or drivers (90), which device (60)is connected to the apparatus (40) for production of a reference voltagevalue, and having a device (50) for comparison of the output voltagevalue with the reference voltage value, in which case the comparisondevice (50) is or can be connected to the driver or drivers (90).
 2. Thearrangement as claimed in claim 1, characterized in that the apparatus(20) for recording the time profile of the output voltage which isemitted from the driver or drivers (90) to a load (12) is in the form ofa window comparator.
 3. The arrangement as claimed in claim 2,characterized in that the window comparator (20) has two voltagecomparators (21, 22), which are connected to an AND gate (23).
 4. Thearrangement as claimed in one of claims 1 to 3, characterized in thatthe apparatus (30) for conversion of the measured time profile of theoutput voltage to an output voltage value has a current source (31), aswitch element (32) and a capacitance (33), in which case the switchelement (32) is operated or can be operated via signals from theapparatus (20) for recording the time profile of the output voltagewhich is emitted from the driver or drivers (90) to a load (12).
 5. Thearrangement as claimed in one of claims 1 to 4, characterized in thatthe apparatus (40) for production of a reference voltage value has acurrent source (41), a switch element (42) and a reference capacitance(43), in which case the switch element (42) is operated or can beoperated via signals from the device (60) for presetting a desired slopetime for the driver or drivers (90).
 6. The arrangement as claimed inone of claims 1 to 5, characterized in that the device (50) forcomparison of the output voltage value with the reference voltage valueis in the form of a comparator.
 7. The arrangement as claimed in one ofclaims 1 to 6, characterized in that an apparatus (51) is provided forselection of the driver strength, in that the apparatus (51) isconnected to the device (50) for comparison of the output voltage valuewith the reference voltage value, and in that the apparatus (51) forselection of the driver strength is or can be connected to the driver ordrivers (90) as well.
 8. The arrangement as claimed in one of claims 1to 7, characterized in that the device (60) for presetting the desiredslope time for the driver or drivers (90) is designed for production ofa square-wave pulse (62), whose length corresponds to the desired slopetime.
 9. The arrangement as claimed in one of claims 1 to 8,characterized in that the device (60) for presetting the desired slopetime for the driver or drivers (90) is designed for processing a systemclock (63).
 10. The arrangement as claimed in one of claims 1 to 9,characterized in that the device (60) for presetting the desired slopetime for the driver or drivers (90) has one or more delay elements (61).11. The arrangement as claimed in one of claims 1 to 10, characterizedin that the device (60) for presetting the desired slope time for thedriver or drivers (90) has at least one phase detector (64).
 12. Thearrangement as claimed in one of claims 1 to 11, characterized in thatthe device (60) for presetting the desired slope time for the driver ordrivers (90) has at least one apparatus (65) for production of a controlvoltage.
 13. The arrangement as claimed in one of claims 1 to 12,characterized in that the device (60) for presetting the desired slopetime for the driver or drivers (90) has at least one switch element(66), in particular a multiplexer, for switching between different slopetime signals.
 14. A driver circuit for driving a load, having one ormore drivers (90) which is or are connected to the load (12),characterized in that the driver or drivers (90) is or are connected toan arrangement (10) for adjustment of the slope times as claimed in oneof claims 1 to
 13. 15. The driver circuit as claimed in claim 14,characterized in that the driver or drivers (90) is or are in the formof a scalable driver or scalable drivers.
 16. The driver circuit asclaimed in claim 15, characterized in that the driver or drivers (90)each has or have one or more partial driver elements (91).
 17. Thedriver circuit as claimed in one of claims 14 to 16, characterized inthat one or more drivers (90) is or are each connected to an arrangement(10) for adjustment of the slope times.
 18. The driver circuit asclaimed in claim 17, in which a number of drivers (90) are connected toan arrangement (10) for adjustment of the slope times, characterized inthat the drivers (90) are connected to the arrangement (10) via a switchelement, in particular a multiplexer.
 19. The driver circuit as claimedin one of claims 14 to 18, characterized in that the load (12) is in theform of a capacitive load.
 20. A method for adjustment of the slopetimes for one or more drivers essentially independently of externalconditions, in particular using an arrangement as claimed in one ofclaims 1 to 13, characterized by the following steps: a) measurement ofthe time profile of an output voltage which is emitted from the driveror drivers to a load; b) conversion of the measured time profile of theoutput voltage to an output voltage value; c) production of a referencevoltage value which is essentially independent of external conditions;d) comparison of the output voltage value with the reference voltagevalue; and e) matching of the driver or drivers as a function of thecomparison results.
 21. The method as claimed in claim 20, characterizedin that the time profile of the output voltage is measured by measuringits rise time and/or its fall time.
 22. The method as claimed in claim20 or 21, characterized in that the measured time profile of the outputvoltage is converted in an apparatus for conversion to an output voltagevalue.
 23. The method as claimed in claim 22, characterized in that theapparatus for conversion of the time profile of the output voltage has acurrent source, a switch element and a capacitance, and in that the timeprofile of the output voltage is converted to an output voltage value byclosing the switch element during a predetermined time period, inparticular during the rise time and/or the fall time of the outputvoltage, and in that, during this time period, the previously dischargedcapacitance is charged by means of the current source to the outputvoltage value.
 24. The method as claimed in one of claims 20 to 23,characterized in that the reference voltage value is produced in anapparatus for production of a reference voltage value, with theapparatus having a current source, a switch element and a referencecapacitance, by the switch element being closed via a device forpresetting a desired slope time, which is essentially independent ofexternal conditions, for the driver or drivers for the duration of avoltage pulse, in particular a square-wave pulse, which is preset by thedevice and whose length corresponds to the desired slope time, and inthat, during this time period, the previously discharged referencecapacitance is charged by means of the current source to the referencevoltage value.
 25. The method as claimed in one of claims 20 to 24,characterized in that the output voltage value and the reference voltagevalue are compared in a comparator, and in that the slope time of theoutput voltage which is emitted to the load is adjusted on the basis ofthese comparison results.
 26. The method as claimed in one of claims 20to 25, characterized in that the individual method steps are repeatedfor production of a control cycle.
 27. Use of an arrangement as claimedin one of claims 1 to 13 for adjustment of one or more drivers, inparticular of one or more pad drivers, for integrated circuits.
 28. Useof a driver circuit as claimed in one of claims 14 to 19 as a driver, inparticular as a pad driver, for integrated circuits.
 29. Use of a methodas claimed in one of claims 20 to 26 for adjustment of one or moredrivers, in particular of one or more pad drivers, for integratedcircuits.